Output buffer having inherently precise data masking

ABSTRACT

A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a reissue of U.S. Pat. No. 5,983,314, issued Nov. 9,1999. More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,983,314. The reissue applications are applicationSer. Nos. 10/006,785 and 10/460,813. Application Ser. No. 10/460,813 isa divisional reissue application of application Ser. No. 10/006,785, nowabandoned.

TECHNICAL FIELD

This invention relates to memory devices, and more particularly to adata output buffer which may be used in a memory device in which a datamasking control signal is inherently synchronized to data coupledthrough the buffer.

BACKGROUND OF THE INVENTION

Output buffers are commonly used in memory devices, such as dynamicrandom access memories (“DRAMs”), to supply data from a location in amemory array to one or more data bit terminals of the memory deviceduring a memory read operation. The data bit terminal is commonlyreferred to as the “DQ” terminal. When a memory location storing a valueof logic “1” is read, the output buffer receives complimentary logic “1”and logic “0” signals at respective DATA and DATA* input terminals andapplies a logic “1” signal (which may be 3.3 volts or 5 volts, forexample) to the DQ terminal. When a memory location storing a value oflogic “0” is read from a memory location, the output buffer receivescomplimentary logic “0” and logic “1” signals at respective DATA andDATA* input terminals and applies a logic “0” signal to the DQ line.Although the prior art output buffers will be described as being acomponent of a DRAM, it will be understood that they are also used indevices other than DRAMs, such as in static random access memories(“SRAMs”).

As output buffers have developed in speed and capability, they have beendesigned to perform additional functions. One of these functions is adata mask operation in which the data output terminal of the outputbuffer is switched to a high impedance or “tri-state” conditionresponsive to a data mask signal, known as a “DQM” signal. During thistri-state condition, the output buffer does not output any signal at theDQ terminal.

The conventional approach to masking a data signal output by a dataoutput buffer is to apply the DQM signal to an active low enable inputof an output buffer 10, as illustrated in FIG. 1. The DQM signal isapplied to the enable output buffer 10 through a register 12 that isenabled by a clock (“CLK”) signal. Thus, the DQM signal is registered tothe edge of the CLK signal, although the DQM signal may be delayed tosome degree in being coupled out of the register 12 to the output buffer10. Similar, and often longer, delays may occur in coupling the DATA andDATA* signals to the output buffer 10.

During a normal read operation, the DQM signal is a logic “0” therebyenabling the output buffer 10. As a result, the output buffer 10 appliesa data output signal to the DQ terminal that correspond to thecomplimentary DATA and DATA* inputs to the output buffer 10.

With reference to FIG. 2, when a masked data read operation is to occur,a logic “1” DQM signal is applied to the enable input of the outputbuffer 10. As is conventional, the output buffer operates with a readlatency, which may be 2 clock cycles as shown in FIG. 2. In a latency of2, an active DQM signal is applied to the output buffer 10 approximately2 clock pulses before the data to be masked are applied to the DATA andDATA* input of the output buffer 10. Thus, the output buffer 10 isdisabled approximately 2 clock pulses after DQM goes high. As a result,the output buffer 10 passes the first two bits of data, but its outputis tri-stated during the third bit of data. Thus, during the time thatDATA2 and DATA2* are applied to the output buffer 10 and the outputbuffer would otherwise output a corresponding DQ signal on the DQterminals of the output buffer 10, the DQ terminal of the output buffer10 becomes essentially open circuited. (The DATA* signal has beenomitted from FIG. 2 since it is simply the compliment of DATA).

The above-described conventional approach to performing a masked dataread operation is satisfactory if the DQM signal is properlysynchronized with the DATA and DATA* signals. Under these circumstances,the output buffer 10 is disabled as illustrated in FIG. 2 in a manner inwhich the entire DATA2 signal is masked, but no part of either DATA1 orDATA3 is masked. However, in practice, particularly at higher operatingspeeds, the DQM signal is often not well synchronized to the DATA andDATA* signals. If an active high DQM signal is applied to the outputbuffer 10 too late relative to the DATA and DATA* signals, then thetrailing part of the data bit prior to the desired data bit will bemasked, and the trailing part of the desired data bit will not bemasked. With reference to FIG. 3, the output buffer 10 is disabled afterthe DQM signal goes high with the same latency delay shown in FIG. 2.However, the DATA and DATA* signals are applied to the output buffer 10later than as shown in FIG. 2. As a result, the trailing portion of theDQ1 bit is improperly masked, and the trailing portion of the DQ2 bit isimproperly not masked. Under these circumstances, the DQ1 bit may bepresent for less than the output hold time t_(OH) specified for a memorydevice using the output buffer 10. Furthermore, the output buffer 10 mayfail to mask the DQ2 bit so that it is read by a processor (not shown)or other device performing the read operation. Although the problemillustrated in FIG. 3 has occurred because of an excessive delay inapplying the DATA and DATA* signals to the output buffer 10, the sameproblem occurs if the DQM signal is applied with insufficient delay(i.e. to early), or any combination of the DATA and DATA* signalsapplied too late and the DQM signal applied too early.

A problem similar to that illustrated in FIG. 3 occurs if the DQM signalis applied to the output buffer 10 too late, the DATA and DATA* signalsare applied to early, or any combination of the two. With reference toFIG. 4, the output buffer 10 is once again disabled after the DQM signalgoes high with the same latency delay shown in FIGS. 2 and 3. However,the DATA and DATA* signals are applied to the output buffer 10 earlierthan as shown in FIG. 2. As a result, the leading portion of the DQ2 bitis improperly not masked, and the leading portion of the DQ3 bit isimproperly masked. Under these circumstances, the DQ3 bit may be presentfor less than the output hold time t_(OH) specified for a memory deviceusing the output buffer 10. Furthermore, the output buffer 10 may onceagain fail to mask the DQ2 bit so that it is read by a processor (notshown) or other device performing the read operation.

Although both of the above-described problems could theoretically besolved by precisely synchronizing the DQM signal to the DATA and DATA*signals as they are applied to the output buffer 10, in practice it isnot possible to synchronize the signals to each other with adequateprecision. Furthermore, the delays are difficult to predict and may varywith time with different memory devices and with different systems usingthe memory devices, thus making it impractical to synchronize the signalto each other by imposing a compensating delay on either the DQM signalor the DATA and DATA* signals. There is thus a need for an output bufferthat is capable of precisely masking the entire portion of a desireddata bit without masking any portion of adjacent data bits.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, an output bufferincludes a data coder adapted to receive complimentary read data signalsand a data mask signal, and an output stage received coded read datasignals from the data coder. The coded read data signals from the datacoder correspond to the complimentary read data signals in the absenceof the data mask signal. The data coder codes the encoded read datasignals in a predetermined manner, such as having the same value ratherthan being complimentary, responsive to the data mask signal. In theevent the coded read data signals are not coded in the predeterminedmanner, the output stage generates on a data output terminal an outputsignal having a value corresponding to the coded read data signals. Ifthe coded read data signals are coded in the predetermined manner, theoutput stage causes its data output terminal to have a high impedance.The data coder preferably includes a data mask register and a dataoutput register coupled to the data mask register. The data coder isadapted to receive the data mask control signal and a periodic clocksignal, and generates an output signal registered to a predeterminedportion of the clock signal after the data mask control signal becomesactive. The data output register forces the coded read data signals tohave the predetermined values responsive to the output signal from thedata mask register. The data mask registers also preferably includes alatency control circuit adapted to receive a latency control signal andto alter the time when the data mask register generates the outputsignal as a function of the latency control signal. The data outputregister preferably includes a multi-phase signal generator receiving aperiodic clock signal and generating from the clock signal a pluralityof differently-phased input data enable signals and output data enablesignals. The data output register preferably further includes aplurality of latches each storing the read data signals responsive to arespective differently-phased input data enable signal and outputtingthe stored read data signals responsive to a respectivedifferently-phased output data enable signal. The output stagepreferably includes a logic circuit that causes the output signalapplied to the data output terminal to have a first logic levelresponsive to one of the coded data read output signals having a firstpredetermined logic level, that causes the output signal applied to thedata output terminal to have a second logic level responsive to theother of the coded data read output signals having a secondpredetermined logic level, and that causes the data output terminal tohave the relatively high impedance responsive to both of the coded readoutput signals having other than the first and second predeterminedlogic levels. The output stage preferably comprises a first switchcoupled between a first voltage node and the data output terminal, and asecond switch coupled between a second voltage node and the data outputterminal. A logic circuit closes the first switch responsive to one ofthe coded data read signals having the first predetermined logic level,opens the first switch responsive to the coded data read signal havingother than the first predetermined logic level, closes the second switchresponsive to the other of the coded data read signals having the secondpredetermined logic level, and opens the second switch responsive to thecoded data read signal having other than the second predetermined logiclevel. The output buffer may be used in a memory device, such as adynamic random access memory, which may be a component of a computersystem having a processor, an input device, an output device, and a datastorage device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art memory device employing a priorart data output buffer.

FIG. 2 is a timing diagram showing signals applied to and received fromthe data output buffer of FIG. 1 in which a data masking control signalis properly synchronized to data coupled though the buffer.

FIG. 3 is a timing diagram showing signals applied to and received fromthe data output buffer of FIG. 1 in which data coupled though the bufferis masked too quickly.

FIG. 4 is a timing diagram showing signals applied to and received fromthe data output buffer of FIG. 1 in which data coupled though the bufferis masked too slowly.

FIG. 5 is a block diagram of a data output buffer according to apreferred embodiment of the invention.

FIG. 6 is a timing diagram showing signals applied to and received fromthe data output buffer of FIG. 5.

FIG. 7 is a schematic and logic diagram of a preferred embodiment of adata output stage used in the data output buffer of FIG. 5.

FIG. 8 is a block diagram of a preferred embodiment of a data coder usedin the data output buffer of FIG. 5.

FIG. 9 is a schematic of a preferred embodiment of a 3-phase signalgenerator used in the data coder of FIG. 8.

FIG. 10 is a timing diagram showing signals applied to and received fromthe 3-phase signal generator of FIG. 9.

FIG. 11 is a schematic of a preferred embodiment of a DQM Register usedin the data coder of FIG. 8.

FIG. 12 is a timing diagram showing signals applied to and received fromthe DQM Register of FIG. 11 for two different read latency values.

FIG. 13 is a schematic of a preferred embodiment of a Data Out Registerused in the data coder of FIG. 8.

FIG. 14 is a timing diagram showing signals applied to and received fromthe Data Out Register of FIG. 13.

FIG. 15 is a block diagram of a computer system including a dynamicrandom access memory (“DRAM”) using the data output buffer of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

A preferred embodiment of an output buffer 20 in accordance with theinvention is illustrated in FIG. 5 and will be explained with referenceto the timing diagram of FIG. 6. The output buffer includes a data coder22 that receives complimentary data signals DATA and DATA* from an arrayin a memory device (not shown in FIG. 5), a periodic clock CLK signal,and a data mask DQM signal. The data coder 22 drives an output stage 24with signals DATA0* and DATA1* that are complimentary except when theoutput stage 24 is to be tri-stated during a data mask operation. Thus,for example, during the period from t₀ to t₂ of FIG. 6, the READ0* andREAD1* signals correspond to the DATA and DATA* signals, respectively.However, it will be noted that the DQM signal goes active high at justprior to time t₄. After a predetermined latency delay period (2 clockcycles in the example of FIG. 6), the READ0* and READ1* signals are nolonger the compliment of each other at time t₅. Instead, during theperiod between t₅ and t₇, the READ0* and READ1* signals are both high.After t₇, the READ0* and READ1* signals once again correspond to theDATA and DATA* signals, and are thus the compliment of each other. Insummary, when the data is not being masked, the READ0* and READ1*signals correspond to the complimentary DATA and DATA* signals. When thedata read from a memory device is to be masked, the READ0* and READ1*signals are identical and thus no longer correspond to the DATA andDATA* signals, respectively.

As further illustrated in FIG. 6, the output stage 24 generates a DQsignal on a DQ output line that corresponds to the READ0* and READ1*signals are complimentary. Thus, during the period to through t₂, the DQsignal corresponds to the DATA signal. However, the output stage 24recognizes that the READ0* and READ1* signals are no longer thecompliment of each other between t₅ and t₇ and, in response thereto,tri-states its DQ output line to a high impedance.

It is important to note that the timing of the tri-state condition isprecisely aligned with the DQ signal even though the DQM signal was notasserted in synchronism with either the CLK signal or the DATA and DATA*signals. By coding the data signals READ0* and READ1* with instructionsto tri-state the DQ output line, the tri-stating of the DQ output lineis inherently aligned with the data to be masked.

A preferred embodiment of the output stage 24 usable in the preferredembodiment of the output buffer 20 of FIG. 5 is illustrated in FIG. 7.The DQ signal is generated at the junction of the source of a first NMOStransistor 30 and the drain of a second NMOS transistor 32. The drain ofthe NMOS transistor 30 is coupled to a supply voltage while the sourceof the NMOS transistor 32 is coupled to ground. Thus, when a pull-up PUsignal applied to the gate of the NMOS transistor 30 is high and apull-down PD signal applied to the gate of the NMOS transistor 32 islow, the transistor 30 is ON and the transistor 32 is OFF, therebydriving the DQ terminal to a logic “1” voltage level. When the pull-upPU signal is low and the pull-down PD signal is high, transistor 30 isOFF and transistor 32 is ON, thereby driving the DQ terminal to a logic“0” voltage level. Finally, when both the pull-up PU signal and thepull-down PD signal are low, both transistors 30 and 32 are OFF, therebytri-stating the DQ terminal to a high impedance level.

The function of the remaining circuitry in the output stage 24 isprimarily to drive the PU and PD signals to correspond to the READ0* andREAD1* signals, respectively, except when the READ0* and READ1* signalsare both high. More specifically, the output stage 24 drives the PUsignal high and the PD signal low when the READ0* signal is high and theREAD1* signal is low. The output stage 24 drives the PU signal low andthe PD signal high when the READ0* signal is low and the READ1* signalis high. Finally, the output stage 24 drives both the PU signal and thePD signal low when the READ0* signal and the R1* signal are both high.The manner in which the output stage 24 performs these functions willnow be explained in detail.

The READ0* and READ1* signals are applied to the inputs of respectivelatches 40, 42, each of which is formed by a pair of inverters 43, 44,through a pair of transmission gates 45, 46 which are selectivelyenabled by a signal at the output of a delay circuit 47 applied directlyand through an inverter 48. The delay circuit 47 is driven by the clockCLK signal through an inverter 49. As explained below, the purpose ofthe transmission gates 45, 46 and associated circuitry is to couple theREAD1* and READ0* signals to the latches 40, 42 at the proper time,i.e., during the ½ clock cycle starting shortly after the clock CLKsignal goes high. For the purpose of explaining the operation of theoutput stage 24, it will be assumed that the transmission gates 45, 46are continuously enabled.

Assuming that the transmission gates are enabled, the READ1* and READ0*signals are applied to the inputs of the latches 40, 42, respectively,which are selectively pulled high by respective PMOS transistors 50, 52each of which are driven by an enable QED signal. During normaloperation, the QED signal is high, thereby turning off the transistors50, 52 to allow the latches 40, 42 to function in a normal manner. Asexplained below, when the QED signal is low, the DQ output line istri-stated. Unless otherwise stated, the operation of the output stage24 will be explained with the understanding that the QED signal is high,thereby enabling the output stage 24.

When the READ0* signal is low, the output of the latch 42 is high,thereby enabling a NAND gate 56. The other input of the NAND gate iscoupled to the output of the latch 40 though an inverter 58. If READ1*is high, the output of the latch 40 is low, thereby causing the inverter58 to output a high to the NAND gate 56. Thus, when the READ0* signal islow and the READ1* signal is high, the NAND gate 56 outputs a low whichcauses an inverter 60 to output a high PD signal to the gate of the NMOStransistor 32, thereby turning on the transistor 32 and pulling the DQterminal low. The low at the output of the latch 40 resulting from thehigh READ1* signal is also applied to an inverter 68 which drives alevel translator circuit 70. The high at the output of the inverter 68turns ON an NMOS transistor 72 in the level translator circuit 70. TheON transistor 72 then pulls the gate of a PMOS transistor 74 and thepull-up PU signal low. The low applied to the gate of the PMOStransistor 74 turns on the transistor 74 to bias the gate of a PMOStransistor 75 high, thereby turning OFF the transistor 75. Although thedrain of an NMOS transistor 76 is driven high by the ON PMOS transistor74, no current is conducted through the transistor 76 since its gate isbiased low through an inverter 78. The low PU signal turns OFF the NMOStransistor 30. Thus, when the READ0* signal is low and the READ1* signalis high, only the transistor 32 is turned on to drive the DQ terminallow.

When the READ0* signal is high, the output of the latch 42 is low,thereby disabling the NAND gate 56. The NAND gate 56 then outputs a highwhich causes the inverter 60 to output a low, thereby making the pulldown PD signal low to turn OFF the transistor 32. If the READ1* signalis low when the READ0* signal is high, the latch 40 outputs a high whichperforms two functions. First, the high at the output of the latch 40causes the inverter 58 to output a low, thereby ensuring that the NANDgate 56 is disabled to turn OFF the transistor 32. Thus, if the READ1*signal is low, the transistor 32 will be turned OFF regardless of thestate of the READ0* signal. Second, the high at the output of the latch40 causes the inverter 68 to output a low, thereby turning OFF the NMOStransistor 72. At the same time, the low at the output of the latch 40causes the inverter 78 to turn ON the transistor 76. The transistor 76then pulls the gate of the PMOS transistor 75 low to turn ON thetransistor 75. As a result, the ON PMOS transistor 75 drives the pull upPU signal high to turn ON the transistor 30 and maintain PMOS transistor74 OFF. Thus, when the READ0* signal is high and the READ1* signal islow, only the transistor 30 is turned on, thereby driving the DQterminal high.

When the READ0* and the READ1* signals are both high, the high READ1*signal turns OFF the transistor 30 in the same manner as explained abovefor the READ0* signal being low and the READ1* signal being high.Similarly, the low at the output of the latch 46 resulting from the highREAD0* signal disables the NAND gate 56, thereby turning OFF thetransistor 32 in the same manner as explained above for the READ0*signal being high and the READ1* signal being low. Thus, when the READ0*and READ1* signals are both high, both of the transistors 30 and 32 areturned OFF, thereby tri-stating the DQ terminal to a high impedance.

As mentioned above, the enable signal QED is normally high to enable theoperation of the output stage 24, and the output stage 24 tri-states itsDQ terminal if the QED signal is low. The low QED signal performs thisfunction because the outputs of both latches 40, 42 are driven lowwhenever the transistors 50, 52, respectively, are turned ON by the lowQED signal. The low at the output of the latch 40 turns OFF thetransistor 30 in the same manner as explained above for the READ0*signal being low and the READ1 * signal being high. Similarly, the lowat the output of the latch 42 turns OFF the transistor 32 in the samemanner as explained above for the READ0* signal being high and theREAD1 * signal being low.

Although the READ0* and READ1* signals both being low is not a validoperational state, it should be recognized that this state will notcause both transistors 30, 32 to be ON. While the low READ1* signal willturn ON the transistor 30 in the same manner as explained above for thecase of READ0* being high and the READ1* being low, the low READ0*signal will not turn ON the transistor 32 in the same manner asexplained above for the case of READ0* being low and the READ1* beinghigh. This is because the low READ1* signal disables the NAND gate 56 sothat the high coupled to the other input of the NAND gate 56 because ofthe low READ0* signal cannot cause the NAND gate 56 to output a low.Instead, the NAND gate 56 outputs a high, thereby turning OFF thetransistor 32. Thus, if the READ0* and the READ1* signals are both low,only the transistor 30 will be turned ON.

In summary, the logic level of the DQ signal at the DQ terminalcorresponds to the logic level of the READ0* signal as long as theREAD0* signal is the compliment of the READ1* signal. If the READ0*signal and the READ1* signal are both high, the DQ terminal istri-stated to a high impedance.

A preferred embodiment of the data coder 22 of FIG. 5 is illustrated inFIG. 8. Complementary data signals DATA and DATA* from a memory array(not shown in FIG. 9) are applied to a data out register 80. The dataout register 80 also receives three phases of enable and data latchsignals from a three phase generator 82. The three phase signals appliedto the data out register 80 are generated by the three phase generator82 from the clock CLK signal. The data out register 80 also receives aDQM out signal from a DQM register 84. Basically, the DQM register 84controls the timing of the DQM-out signal responsive to a DQM inputsignal with a read latency determined by a CL1 input. The DQM register84 also receives the clock CLK signal to control the timing of theDQM-out signal. In response to the complementary data signals DATA andDATA* and the signals received from the three phase generator 82 and DQMregister 84, the data out register 80 generates the READ0* AND READ1*signals having the characteristics described above with reference to theoutput stage 24. In particular, in the absence of a DQM signal, theREAD0* and READ1* signals correspond to the DATA and DATA* signals.However, in response to a DQM signal, the READ0* and READ1*, the dataoutput register 80 drives both the READ0* signal and the READ1* signalhigh at the appropriate time to cause the DQ output of the terminalstage 24 (FIG. 5) to have a high impedance.

A preferred embodiment of the three phase signal generator 82 isillustrated in FIG. 9. The operation of the three phase signal generator82 will be explained with reference to the timing diagram of FIG. 10 inwhich various signal nodes in FIG. 9 have been designated withcorresponding reference letters. The clock signal on node A is appliedto a NAND gate 90, both directly and through a delay circuit 92, and aninverter 94. The delayed and inverted clock signal is shown as signal“B” in FIG. 10. The output of the NAND gate 90 (signal C) is high exceptfor a short period at the leading edge of the clock signal for aduration corresponding to the duration of the delay circuit 92. Theoutput of the NAND gate 90 is applied to a NAND gate 98 which isconnected to a second NAND gate 100 to form a flip-flop. The flip-flop100 is initially held in a reset condition by RST* being low which isapplied to the input of the NAND gate 100. Thus, the output of the NANDgate 100 is initially high which is coupled through a delay circuit 102to disable a NOR gate 104. Thus, the output of the NOR gate 104 (node H)is initially at a stable low value.

The clock's CLK signal is also applied to a NAND gate 110 both directlyand through a delay circuit 112. The output of the delay circuit 112, asshown as signal D in FIG. 11, is simply a delayed version of the clockCLK signal. The NAND gate 110 outputs at node E a signal that is highexcept for the portion of the clock signal following the delayestablished by the delay circuit 112. This signal at node E is appliedthrough an inverter 114 to the other input of the NOR gate 104. Theoutput of the inverter 114 is shown as signal “F” in FIG. 10. Theperiodic signal at the output of the inverter 114 initially has noeffect on the remainder of the three phase signal generator illustratedin FIG. 9 because, as explained above, the NOR gate 104 is disableduntil the flip-flop formed by the NAND gates 98, 100 is set.

As mentioned above, the reset RST* signal is initially active low. ThisRST* signal is applied through an inverter 118 to generate signals forcontrolling the initial condition of a closed loop of latches 120. Afirst latch 122 is formed by a pair of inverters 124, 126 connected toeach other input-to-output, and an input transmission gate 128. Theoutput of the latch 122 is coupled through an inverter 130 to generate afirst enable signal EN1. A second latch 132 is formed by a pair ofinverters 134, 136 connected to each other input-to-output and to aninput transmission gate 138 in the same manner as explained above withreference to the latch 122. The output of the latch 132 is coupledthrough a pair of inverters 140, 142 to generate a first data inputsignal EN1D. Similarly, a third latch 150 is formed by a pair ofinverters 152, 154, and an input transmission gate 156. The output ofthe latch 150 is coupled through an inverter 158 to generate a secondenable signal EN2. A fourth latch 160 is formed by inverters 162, 164and a transmission gate 166, and outputs through inverters 168, 170 asecond data input signal EN2D. Still another latch 174 is formed by apair of inverters 176, 178 and an input transmission gate 180, andoutputs through an inverter 182 a third enable signal EN3. Finally, asixth latch 186 is formed by a pair of inverters 188, 190 and an inputtransmission gate 192. The output of the latch 186 is coupled through apair of inverters 196, 198 to generate a third data input signal EN3D.The output of the latch 186 is also coupled back to the inputtransmission gate 128 of the first latch 122.

As mentioned above, the initial conditions of the loop 120 arecontrolled by the reset RST* signal and its complement at the output ofthe inverter 118. The high at the output of the inverter 118 is appliedto the gates of a pair of NMOS transistors 200, 202 to cause respectivelatches 150, 174 to output a logic “1” which causes EN2 and EN3 to below, as illustrated in FIG. 10. The RST* signal is also applied to thegate of a PMOS transistor 204 which causes the latch 122 to output alogic “0” thereby causing EN1 to be high, as illustrated in FIG. 10.Also, since the output of the NOR gate 104 (node H) is initially low,the output of the NOR gate 104 and its complement at the output of aninverter 208 enable the transmission gates 138, 166 and 192. As aresult, the output of the latch 122 is coupled to the input of the latch132 thereby making EN1D initially high, as illustrated in FIG. 10. In asimilar manner, the output of the latch 150 is coupled through the passgate 166 to the latch 160 and the output of the latch 174 is coupledthrough transmission gate 192 to the latch 186, thereby making EN2D andEN3D initially low.

The operation of the three phase signal generator 82 departs from itsinitial conditions when the RST* signal goes inactive high at t₀, asillustrated in FIG. 10. The high RST* removes the reset from the NANDgate 100 so that the output of the NAND gate 90 (signal C) can set theflip-flop formed by NAND gates 98, 100 at the next leading edge of theclock at t₁. After a short delay produced by the delay circuit 102, theNOR gate 104 is enabled by the input to the NOR gate (signal G) goinglow at t₂. Thereafter, the periodic signal at the output of the inverter114 (signal F) is coupled through the NOR gate 104. Whenever the outputof the NOR gate 104 (signal H) goes low, the transmission gates 138, 166and 192 are enabled. Whenever the output of the NOR gate 104 goes high,the transmission gates 128, 156 and 180 are enabled. Thus, at time t₃,the low at the output of the latch 186 is coupled through thetransmission gate 128 to cause EN1 to go low. At the same time, the highat the output of the latch 132 is coupled through the transmission gate156 to cause EN2 to go high. Although the transmission gate 180 alsocouples the output of the latch 160 to the latch 174 at this time, sincethe output of the latch 162 was low and the input of the latch 174 wasinitially held low by the NMOS transistor 202, the state of the EN3signal does not change. Although the EN1 and EN2 signals transition att₃, those transitions do not affect the EN1D and EN2D signals becausethe transmission gates 138 and 164 are disabled at t₃ when the output ofthe NOR gate 104 goes high.

When the output of the NOR gate 104 (signal H) goes low at time t₄, thetransmission gate 138, 166 and 192 are enabled while the transmissiongates 128, 136, 164 are disabled. As a result, the high at the output oflatch 122 is coupled to the input of the latch 132 thereby causing theEN1D signal to go low. At the same time, the low at the output of thelatch 150 is coupled to the input of the latch 160, thereby causing theEN2D signal to go high. In a similar manner, the high EN2 and EN2Dsignals propagate through the latches so that only one of the enablesignals EN1-EN3 is high, with the enable signals being equally phasedfrom each other. Similarly, only one of the data input signals EN1D-EN3Dis high at a time, with the data input signals being equally phased fromeach other. As explained below, these three phase enable and data inputsignals are used by the data out register 80 (FIG. 8) to retain the datasignals DATA and DATA* for the proper period to account for a readlatency and then apply the READ0* and READ1* signals to the output stage24 (FIG. 5) at the appropriate time.

A schematic of the DQM register 84 (FIG. 8) is illustrated in FIG. 11and explained with reference to the timing diagram of FIG. 12. Theprimary purpose of the DQM register 84 is to register the DQM-out signalat either the rising edge or the falling edge of the clock CLK signal,depending on whether the read latency is two or three. As a result,unpredictable delays of the DQM signal are compensated for since theDQM-out signal is always generated at the rising edge or the fallingedge of the clock CLK signal. The DQM signal is applied to a first latch220 formed by a pair of inverters 222, 224 connected input-to-output andan input transmission gate 226. The output of the first latch 220 isapplied to a second latch 230 formed by an inverter 232 and a NAND gate234 connected output-to-input and an input transmission gate 236. Inoperation, the NAND gate 234 functions as an inverter when it is enabledby a high enable QED signal. The output of the latch 230 is appliedthrough an inverter 238 to a third latch 240 also formed by an inverter242, a NAND gate 244 and an input transmission gate 246.

The initial conditions of the latches 220, 230, 240 are determined by aRESET input. The RESET input is applied to the gate of an NMOStransistor 250 which forces the output of the latch 220 high when RESETis active high. The RESET input is also applied through an inverter 252to the gates of respective PMOS transistors 254, 256. The PMOStransistors 254, 256 force the output of the latches 230, 240 low whenRESET is active high. Thus, the output of the first latch 220 isinitially high while the output of the second and third latches 230,240, respectively, is initially low, as illustrated in FIG. 12.

The transmission gates 226, 236, 246 are selectively enabled by theclock CLK signal and its complement present at the output of an inverter260. The first and third transmission gates 226, 246 are simultaneouslyenabled, while the second transmission gate 236 is enabled when thefirst and third transmission gates 226, 246 are disabled.

The remaining input signal CL1 is used to control the timing of theDQM-out signal depending upon the read latency of a memory device usingthe inventive output buffer. The CL1 signal and its complement at theoutput of an inverter 264 are applied to two transmission gates 266,268. When CL1 is low, the transmission gate 266 is enabled and thetransmission gate 268 is disabled, so that the output of the latch 230is coupled through the transmission gate 266 and a pair of inverters272, 274 to the DQM-output terminal. When CL1 is high, the output of thelatch 240 is coupled through the transmission gate 268 and the inverters272, 274.

In operation, the DQM register 84 remains in its initial state forced bythe RESET as illustrated in FIG. 12. When RESET goes low at t₀, thevalues of the latches 220, 230, 240 are no longer forced at theirinitial values. However, as long as DQM remains low, the condition ofthe latches 220, 230, 240 do not change since the input to the inverter224 in the latch 220 was initially set low and remains low when the lowDQM signal is coupled through the transmission gate 226. However, whenDQM goes high at t₁, the high is coupled through the transmission gate226 on the next rising edge of the clock at t₂. On the next falling edgeof the clock at t₃, the low at the output of the latch 220 is coupledthrough the transmission gate 236 to cause the output of the latch 230to go high. In the event CL1 is low, the high output of the latch 230 iscoupled through the transmission gate 266 and the inverters 272, 274 tocause the DQM-out signal to go high at t₃, as illustrated in FIG. 12. Onthe next rising edge of the clock CLK signal at t₄, the high at theoutput of the latch 230 is coupled through the inverter 238 and thetransmission gate 246 to cause the output of the latch 240 to go high.In the event that CL1 is high, the high at the output of the latch 240is coupled through the transmission gate 268 and inverters 272, 274 tocause the DQM-out signal to go high at t₄.

It is thus seen that, once the active high RESET signal is removed, theDQM register functions to drive the DQM-out signal high on either thefalling edge of CLK (if CL1 is low) or the second rising edge of CLK (ifCL1 is high) after DQM goes high regardless of the exact timing of theDQM signal. As explained below, this delay in generating DQM out isadapted to correspond to the read latency of a memory device in whichthe output buffer is used.

A schematic of the DATA OUT register 80 (FIG. 8) is shown in FIG. 13 andexplained with reference to the timing diagram of FIG. 14. The DATAOUTPUT register 80 includes three registers 300, 302, 304, each of whichincludes a first latch 308 and a second latch 310. Each of the latches308, 310 is formed by a pair of inverters 312, 314 connectedinput-to-output, an input transmission gate 316 and an outputtransmission gate 318. The input transmission gates 316 are selectivelyenabled by respective data input signals EN1D-EN3D and their complementsapplied through respective inverters 330. When the respective data inputsignal EN1D-EN3D is high, the complement of the data signal DATA* isrecorded in the latch 308 while the DATA signal is recorded in the latch310.

The data registers 300, 302, 304 each operate in a similar manner.Specifically, the output of the latches 308, 310 are coupled throughrespective output transmission gates 318 when they are enabled byrespective enable signals EN1-EN3 and their complements at the output ofrespective inverters 334. The output of the latches 308 are coupled to afirst input of a NOR gate 340 while the outputs of the second latches310 are applied to a first input of a second NOR gate 342. The secondinputs of the NOR gates 340, 342 are coupled to the DQM-out terminal.The outputs of the NOR gates 340, 342 are coupled through respectiveinverters 346, 348 to generate the READ0* and READ1* signals,respectively.

In operation, the registers 300, 302, 304 are set to an initialcondition by the RESET signal. Specifically, the RESET signal is appliedto the gates of respective NMOS transistors 360 in each of the latches308, 310. When reset is high, the transistors 360 are turned on to forcethe outputs of the latches 308, 310 high. With reference to FIG. 14, thedata signals DATA and DATA* are coupled to each of the registers 300,302, 304 by the respective data input enable signals EN1D-EN3D beinghigh, and latched into each of the registers 300, 302, 304 whenEN1D-EN3D, respectively each go low. The latched DATA and DATA signalsare coupled out of the registers 300, 302, 304 by the respective dataoutput enable signals EN1-EN3 being high. The data applied to the DATAOUT register 80 is present only during the period that the clock CLKsignal is low. When the clock CLK signal is high, the data inputs float.Thus, at t₀, a first bit of data D0 is latched into the register 304 bythe EN3D signal going low. Subsequently, at time t₁, a second bit ofdata is latched into the register 300 by the EN1D signal going low. Attime t₃, a third bit of data D2 is latched into the register 302 by theEN2D signal going low. Note that, at t₁, t₃, t₅ when the respective datainput enable signal EN1D-EN3D goes low, the corresponding enable signalEN1-EN3, respectively, is low so that data latched into the registers300-304 is not immediately coupled to the outputs of the registers 300,302, 304. Instead, the data coupled into the registers 300-304 is notcoupled to their respective outputs until its respective enable signalEN1-EN3 goes high. Thus, it is not until t₂ when EN3 goes high that thefirst bit of data D0 is coupled out of the first register 300. Likewise,it is not until t₄ when the data bit D1 is coupled out of the secondregister 300 responsive to EN1 going high. Thus, it is apparent fromFIG. 14 that data is coupled out of the data output register 80 on theREAD0* and READ1* lines at least one and one-half clock periods afterthe DATA and DATA* signals have been applied to the data out register80. This delay compensates for the read latency of a memory device withwhich the output buffer is used, as explained below. Note also, that theinput data applied to the inputs of the registers 300, 302 and 304 iscoupled directly to their respective outputs when data is initiallycoupled to each register. Thus, for example, at t₁, the inputtransmission gate 316 and the output transmission gate 318 for theregister 302 are both enabled by the high EN2D and EN2 signals,respectively. However, the data output from the register 302, and theresulting READ0* and READ1* signals, are blocked by the transmissiongates 45, 46 (FIG. 7) during this time. Thus, data applied to theregisters 300, 302, 304 is not effectively applied to the DATA-OUTterminal until after the delay, explained above.

The foregoing explanation assumes that the DQM-OUT input to the dataoutput register 80 is low, thereby enabling the NOR gates 340, 342.However, if the DQM-OUT signal goes high, the outputs of the NOR gates340, 342 are forced low, thereby forcing READ0* and READ1* high. Asexplained above, when READ0* and READ1* are both high, they force theoutputs of the output stage 24 (FIG. 5) to a tristate condition. Becauseof the delay and precise registry with the clock CLK signal of the DQMregister 84 generating the DQM-OUT signal responsive to the DQM signal,the READ0* and READ1* signals are forced high when the correct datasignals to be masked are being output from the respective register 300,302, 304. However, as explained above with reference to FIG. 11, thetiming of the DQM-OUT signal can be adjusted by one-half of a clockperiod depending upon the read latency of the memory device with whichthe output buffer 20 is used.

A computer system 360 using a dynamic random access memory (DRAM) 362having the preferred embodiment of the data output buffer 20 isillustrated in FIG. 15. The computer system 360 includes a conventionalmicroprocessor 364 having a processor bus 366 which normally includesseparate data, address and control/status busses. The processor bus 366is connected through a conventional bus bridge 368 to an input device,such as a keyboard 370, and to an output device, such as a display 372,and to a mass storage device, such as a hard drive 374. The address andcontrol/status buses of the processor bus 366 are also connected to aconventional memory controller 378. The memory controller 378selectively outputs an address on an address bus 380 and a set ofcontrol and status signals on a control/status bus 382. The portion ofthe processor bus 366 constituting a data bus 386 is coupled to the databus of the DRAM 362.

The DRAM 362 includes a control logic circuit 390 which generatesvarious commands from the control signals received via bus 382. One ofthese signals is the data output mask DQM signal. The DRAM 362 alsoincludes an address register 394 which couples an address received onthe bus 380 to either a column decoder 396 or to a row address latch398. A row address output from the row address latch 398 is decoded by arow decoder 400 which selects a corresponding row of memory cells in amemory array 402. A particular column of memory cells in the selectedrow is determined by the column signals output from the column decoder396 which are coupled to the array 402 through an I/O circuit 406 whichnormally includes sense amplifiers, equilibration circuits, writedrivers and the like. Data to be written into the array 402 is coupledthrough a data input buffer 410 to the I/O circuit 406 which then writesthe data into the selected column of the selected row of memory cells inthe array 402. Data is read from the array 402 by the I/O circuit 406which then couples the data through the data output buffer to the databus 386. As explained above, the data output buffer 20 includes a DQMinput which causes the output of the data output buffer to assume a highimpedance state. The computer system 360 shown in FIG. 15, including theDRAM 362, includes a significant amount of additional circuitry whichhas been omitted for purposes of brevity since such circuitry isconventional and is peripheral to the data output buffer 20.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. An output buffers , comprising: a data coder having complimentarydata input terminals, a pair of data read output terminals, and a datamask control terminal, the data coder generating at respective first andsecond data read output terminals complimentary data read output signalscorresponding to complimentary data input signals applied to respectivedata input terminals when an inactive data mask control signal isapplied to the data mask control terminal, the data coder generating atthe respective first and second data read output terminals data readoutput signals having predetermined values when an active data maskcontrol signal is applied to the data mask control terminal, the datacoder comprising: a data mask register including the data mask controlterminal, the data mask register receiving the data mask control signalon the data mask control terminal and a periodic clock signal on a clockinput terminal, the data mask register generating an output signalresponsive to a predetermined portion of the clock signal after the datamask control signal becomes active; and a data output register coupledto the data mask register and including the data input terminals and thedata read output terminals, the data output register forcing the dataread output signals to have the predetermined values responsive to theoutput signal from the data mask register; and an output stage havingrespective input terminals coupled to the first and second data readoutput terminals of the data coder, the output stage generating a dataoutput signal at an output terminal that corresponds to the data readoutput signals from the data coder when the data read output signals donot have the predetermined values, the output stage producing arelatively high impedance at the data output terminal when the data readoutput signals have the predetermined values.
 2. The output buffer ofclaim 1 wherein the predetermined values of the data read output signalsare any values in which the data read output signals at the respectivefirst and second data read output terminals have the same value.
 3. Theoutput buffer of claim 2 wherein the predetermined values of the dataread output signal correspond to logic “1”.
 4. The output buffer ofclaim 1 wherein the data mask register further comprises a latencycontrol terminal adapted to receive a latency control signal, the datamask register altering the time when the data mask register generatesthe output signal as a function of the latency control signal.
 5. Theoutput buffer of claim 1 wherein the data output register comprises amulti-phase signal generator receiving a periodic clock signal andgenerating from the clock signal a plurality of differently-phasedenable and data input signals, and wherein the data output registerfurther comprises a plurality of latches each receiving a respectivedifferently-phased enable signal and a respective differently-phaseddata input signal, the latches being selectively coupled to the datainput terminals responsive to their respective data input signals andbeing coupled to the data output terminal responsive to their respectiveenable signals, the data input signals being sequentially stored in eachof the latches and being sequentially transferred from each of thelatches to the data output terminals after being stored in each of thelatches for a predetermined period.
 6. The output buffer of claim 5wherein the time that the data mask register generates the output signalafter the data mask control signal becomes active corresponds to thepredetermined period that the data input signals are stored in each ofthe latches.
 7. An output buffer, comprising: a data coder havingcomplimentary data input terminals, a pair of data read outputterminals, and a data mask control terminal, the data coder generatingat respective first and second data read output terminals complimentarydata read output signals corresponding to complimentary data inputsignals applied to respective data input terminals when an inactive datamask control signal is applied to the data mask control terminal, thedata coder generating at the respective first and second data readoutput terminals data read output signals having predetermined valueswhen an active data mask control signal is applied to the data maskcontrol terminal, the data coder having a data mask register, the datamask register including the data mask control terminal, the data maskregister receiving the data mask control signal on the data mask controlterminal and a periodic clock signal on a clock input terminal, theregister generating an output signal responsive to a predeterminedportion of the clock signal after the data mask control signal becomesactive, the data mask register having a latency control terminal adaptedto receive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal, the data coder further includinga data output register coupled to the data mask register and having thedata input terminals and the data read output terminals, the data coderforcing the data read output signals to have the predetermined valuesresponsive to the output signal from the data mask register; and anoutput stage having respective input terminals coupled to the first andsecond data read output terminals of the data coder, the output stagegenerating a data output signal at an output terminal that correspondsto the data read output signals from the data coder when the data readoutput signals do not have the predetermined values, the output stageproducing a relatively high impedance at the data output terminal whenthe data read output signals have the predetermined values, the outputstage comprising: a first switch coupled between a first voltage nodeand the data output terminal; a second switch coupled between a secondvoltage node and the data output terminal; and a logic circuit that isstructured to close the first switch responsive to one of the data readsignals having the first predetermined logic level, open the firstswitch responsive to the one data read signal having other than thefirst predetermined logic level, close the second switch responsive tothe other of the data read signals having the second predetermined logiclevel, and open the second switch responsive to the other data readsignal having other than the second predetermined logic level so thatthe data output signal has a first logic level responsive to one of thedata read output signals having a first predetermined logic level, thedata output signal has a second logic level responsive to the other ofthe data read output signals having a second predetermined logic level,and the data output terminal has the relatively high impedanceresponsive to both of the read output signals having other than thefirst and second predetermined logic levels, respectively.
 8. An outputbuffer, comprising: a data mask register including a control terminaladapted to receive a DQM signal, the data mask register generating anoutput signal a predetermined period after receipt of the DQM signal,the data mask register further having a latency control terminal adaptedto receive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal; a data output register coupledto the data mask register and including a pair of complimentary datainput terminals adapted to receive complimentary data input signals anda pair of data output terminals, the data output register generatingrespective output signals on the data output terminals havingpredetermined values responsive to receiving the output signal from thedata mask register and having complimentary values corresponding to thedata input signals at least part of the time that the output signal fromthe data mask register is not being received; and an output stage havingrespective input terminals coupled to the first and second data outputterminals of the data output register, the output stage generating adata output signal at an output terminal that corresponds to the outputsignals from the data output register when the output signals from thedata output register do not have the predetermined values, the outputstage producing a relatively high impedance at the data output terminalwhen the output signals from the data output register have thepredetermined values.
 9. The output buffer of claim 8 wherein thepredetermined values of the output signals from the data output registerare any values in which the output signals at the respective first andsecond data output terminals have the same value.
 10. The output bufferof claim 9 wherein the predetermined values of the output signals fromthe data output register correspond to logic “1”.
 11. The output bufferof claim 9 wherein the data output register generates the output signalson the respective data output terminals having predetermined valuescontemporaneously with receiving the output signal from the data maskregister.
 12. The output buffer of claim 8 wherein the data maskregister further comprises a latency control terminal adapted to receivea latency control signal, the data mask register altering the time whenthe data mask register generates the output signal as a function of thelatency control signal.
 13. The output buffer of claim 8 wherein thedata output register comprises a multi-phase signal generator receivinga periodic clock signal and generating from the clock signal a pluralityof differently-phased data output enable and data input enable signals,and wherein the data output register further comprises a plurality oflatches each receiving a respective differently-phased data input enablesignal and a respective differently-phased data output enable signal,the latches being selectively coupled to the data input terminals of thedata output register responsive to their respective data input enablesignals and being coupled to the data output terminal responsive totheir respective data output enable signals, the data input signalsbeing sequentially stored in each of the latches and being sequentiallytransferred from each of the latches to the data output terminals afterbeing stored in each of the latches for a predetermined period.
 14. Theoutput buffer of claim 13 wherein the time that the data mask registergenerates the output signal after receiving the DQM signal correspondsto the predetermined period that the data input signals are stored ineach of the latches.
 15. The output buffer of claim 8 wherein the outputstage comprises a logic circuit that causes the data output signal tohave a first logic level responsive to one of the output signals fromthe data output register having a first predetermined logic level, thatcauses the data output signal to have a second logic level responsive tothe other of the output signals from the data output register having asecond predetermined logic level, and that causes the data outputterminal to have the relatively high impedance responsive to both of theoutput signals from the data output register having other than the firstand second predetermined logic levels.
 16. The output buffer of claim 15wherein the output stage comprises: a first switch coupled between afirst voltage node and the data output terminal; a second switch coupledbetween a second voltage node and the data output terminal; and whereinthe logic circuit closes the first switch responsive to one of theoutput signals from the data output register having the firstpredetermined logic level, opens the first switch responsive to theoutput signals from the data output register having other than the firstpredetermined logic level, closes the second switch responsive to theother of the output signals from the data output register having thesecond predetermined logic level, and opens the second switch responsiveto the output signals from the data output register having other thanthe second predetermined logic level.
 17. A dynamic random access memoryhaving an address bus, at least one data bit line, and a plurality ofcontrol lines, comprising: an array of memory cells having a pluralityof memory cells, a plurality of row lines, a plurality of complimentarydigit lines, and a pair of complimentary data ports; a row addressdecoder coupled to the address bus, the row address decoder adapted toreceive a row address on the address bus and activate a correspondingone of the row lines of the array; a column address decoder coupled tothe address bus, the column address decoder adapted to receive a columnaddress on the address bus and couple a corresponding pair ofcomplimentary digit lines of the array to respective data ports of thearray; and a data path coupled between the data ports and a data bitline, the data path including a input data buffer adapted to convert aninput data bit applied to the data bit line to a corresponding inputdata signal and a complimentary input data signal, and to apply theinput data signals to respective data ports of the array, and an outputdata buffer adapted to convert an output data signal and a complimentaryoutput data signal applied to respective data ports of the array to anoutput data bit corresponding to the output data signal, and to applythe output data signal to the data bit line, the output buffercomprising: a data coder having complimentary data input terminalscoupled to the data ports of the array to receive respective output datasignals, a pair of data output terminals, and a data mask controlterminal, the data coder generating at respective first and second dataoutput terminals complimentary data read output signals corresponding tocomplimentary data output signals applied to the respective inputterminals of the data coder when an inactive data mask control signal isapplied to the data mask control terminal, the data coder generating atthe respective first and second data output terminals data read outputsignals having predetermined values when an active data mask controlsignal is applied to the data mask control terminal, the data codercomprising: a data mask register including the data mask controlterminal, the data mask register receiving the data mask control signalon the data mask control terminal and a periodic clock signal on a clockinput terminal, the register generating an output signal responsive to apredetermined portion of the clock signal after the data mask controlsignal becomes active, the data mask register further having a latencycontrol terminal adapted to receive a latency control signal, the datamask register altering the time when the data mask register generatesthe output signal as a function of the latency control signal; and adata output register coupled to the data mask register and including thedata input terminals and the data read output terminals, the data coderforcing the data read output signals to have the predetermined valuesresponsive to the output signal from the data mask register; and anoutput stage having respective input terminals coupled to the first andsecond data output terminals of the data coder, the output stagegenerating the output data bit at data bit line that corresponds to thedata read output signals from the data coder when the data read outputsignals do not have the predetermined values, the output stage producinga relatively high impedance at the data bit line when the data readoutput signals have the predetermined values.
 18. The dynamic randomaccess memory of claim 17 wherein the predetermined values of the dataread output signals are any values in which the data read output signalsat the respective data output terminals of the data coder have the samevalue.
 19. The dynamic random access memory of claim 18 wherein thepredetermined values of the data read output signal correspond to logic“1”.
 20. The dynamic random access memory of claim 17 wherein the datamask register further comprises a latency control terminal adapted toreceive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal.
 21. The dynamic random accessmemory of claim 17 wherein the data output register comprises amulti-phase signal generator receiving a periodic clock signal andgenerating from the clock signal a plurality of differently-phased inputdata enable signals and output data enable signals, and wherein the dataoutput register further comprises a plurality of latches each receivinga respective differently-phased input data enable signal and arespective differently-phased output data enable signal, the latchesbeing selectively coupled to the data input terminals responsive totheir respective input data enable signals and being coupled to the dataread output terminals responsive to their respective output data enablesignals, the output data signals from the data ports of the array beingsequentially stored in each of the latches and being sequentiallytransferred from each of the latches to the data read output terminalsafter being stored in each of the latches for a predetermined period.22. The dynamic random access memory of claim 21 wherein the time thatthe data mask register generates the output signal after the data maskcontrol signal becomes active corresponds to the predetermined periodthat the output data signals from the data ports of the array are storedin each of the latches.
 23. A dynamic random access memory having anaddress bus, at least one data bit line, and a plurality of controllines, comprising: an array of memory cells having a plurality of memorycells, a plurality of row lines, a plurality of complimentary digitlines, and a pair of complimentary data ports; a row address decodercoupled to the address bus, the row address decoder adapted to receive arow address on the address bus and activate a corresponding one of therow lines of the array; a column address decoder coupled to the addressbus, the column address decoder adapted to receive a column address onthe address bus and couple a corresponding pair of complimentary digitlines of the array to respective data ports of the array; and a datapath coupled between the data ports and a data bit line, the data pathincluding a input data buffer adapted to convert an input data bitapplied to the data bit, line to a corresponding input data signal and acomplimentary input data signal and to apply the input data signals torespective data ports of the array, and an output data buffer adapted toconvert an output data signal and a complimentary output data signalapplied to respective data ports of the array to an output data bitcorresponding to the output data signal, and to apply the output datasignal to the data bit line, the output buffer comprising: a data coderhaving complimentary data input terminals coupled to the data ports ofthe array to receive respective output data signals, a pair of dataoutput terminals, and a data mask control terminal, the data codergenerating at respective first and second data output terminalscomplimentary data read output signals corresponding to complimentarydata output signals applied to the respective input terminals of thedata coder when an inactive data mask control signal is applied to thedata mask control terminal, the data coder generating at the respectivefirst and second data output terminals data read output signals havingpredetermined values when an active data mask control signal is appliedto the data mask control terminal, the data coder having a data maskregister including the data mask control terminal, the data maskregister receiving the data mask control signal on the data mask controlterminal and a periodic clock signal on a clock input terminal, theregister generating an output signal responsive to a predeterminedportion of the clock signal after the data mask control signal becomesactive, the data mask register further including a latency controlterminal adapted to receive a latency control signal, the data maskregister altering the time when the data mask register generates theoutput signal as a function of the latency control signal, the datacoder further having a data output register coupled to the data maskregister and including the data input terminals and the data read outputterminals, the data coder forcing the data read output signals to havethe predetermined values responsive to the output signal from the datamask register; and an output state having respective input terminalscoupled to the first and second data output terminals of the data coder,the output stage generating the output data bit at data bit line thatcorresponds to the data read output signals from the data coder when thedata read output signals do not have the predetermined values, theoutput stage producing a relatively high impedance at the data bit linewhen the data read output signals have the predetermined values, theoutput stage comprising: a first switch coupled between a first voltagenode and the output data bit; a second switch coupled between a secondvoltage node and the output data bit; and a logic circuit that isstructured to close the first switch responsive to one of the data readsignals having the first predetermined logic level, open the firstswitch responsive to the one data read signal having other than thefirst predetermined logic level, close the second switch responsive tothe other of the data read signals having the second predetermined logiclevel, and open the second switch responsive to the other data readsignal having other than the second predetermined logic level so thatthe output data bit has a first logic level responsive to one of thedata read output signals having a first predetermined logic level, theoutput data bit has a second logic level responsive to the other of thedata read output signals having a second predetermined logic level, andthe data bit line has the relatively high impedance responsive to bothof the read output signals having other than the first and secondpredetermined logic levels, respectively.
 24. A computer system,comprising: a processor having a processor data bus, address bus, andcontrol bus; an input device coupled to the processor; an output devicecoupled to the processor; a memory controller coupled to the processor;and a dynamic random access memory having an address bus, at least onedata bit line, and a plurality of control lines at least some of whichare coupled to the memory controller, the dynamic random access memorycomprising: an array of memory cells having a plurality of memory cells,a plurality of row lines, a plurality of complimentary digit lines, anda pair of complimentary data ports; a row address decoder coupled to theaddress bus, the row address decoder adapted to receive a row address onthe address bus and activate a corresponding one of the row lines of thearray; a column address decoder coupled to the address bus, the columnaddress decoder adapted to receive a column address on the address busand couple a corresponding pair of complimentary digit lines of thearray to respective data ports of the array; and a data path coupledbetween the data ports and a data bit line, the data path including ainput data buffer adapted to convert an input data bit applied to thedata bit line to a corresponding input data signal and a complimentaryinput data signal, and to apply the input data signals to respectivedata ports of the array, and an output data buffer adapted to convert anoutput data signal and a complimentary output data signal applied torespective data ports of the array to an output data bit correspondingto the output data signal, and to apply the output data signal to thedata bit line, the output buffer comprising: a data coder havingcomplimentary data input terminals coupled to the data ports to thearray to receive respective output data signals, a pair of data outputterminals, and a data mask control terminal, the data coder generatingat respective first and second data output terminals complimentary dataread output signals corresponding to complimentary data output signalsapplied to the respective input terminals of the data coder when aninactive data mask control signal is applied to the data mask controlterminal, the data coder generating at the respective first and seconddata output terminals data read output signals having predeterminedvalues when an active data mask control signal is applied to the datamask control terminal, the data coder comprising: a data mask registerincluding the data mask control terminal, the data mask registerreceiving the data mask control signal on the data mask control terminaland a periodic clock signal on a clock input terminal, the registergenerating an output signal responsive to a predetermined portion of theclock signal after the data mask control signal becomes active, the datamask register further having a latency control terminal adapted toreceive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal; and a data output registercoupled to the data mask register and including the data input terminalsand the data read output terminals, the data coder forcing the data readoutput signals to have the predetermined values responsive to the outputsignal from the data mask register and an output stage having respectiveinput terminals coupled to the first and second data output terminals ofthe data coder, the output stage generating the output data bit at databit line that corresponds to the data read output signals from the datacoder when the data read output signals do not have the predeterminedvalues, the output stage producing a relatively high impedance at thedata bit line when the data read output signals have the predeterminedvalues.
 25. The computer system of claim 24 wherein the predeterminedvalues of the data read output signals are any values in which the dataread output signals at the respective data output terminals of the datacoder have the same value.
 26. The computer system of claim 25 whereinthe predetermined values of the data read output signal correspond tologic “1”.
 27. The computer system of claim 24 wherein the data maskregister further comprises a latency control terminal adapted to receivea latency control signal, the data mask register altering the time whenthe data mask register generates the output signal as a function of thelatency control signal.
 28. The computer system of claim 24 wherein thedata output register comprises a multi-phase signal generator receivinga periodic clock signal and generating from the clock signal a pluralityof differently-phased input data enable signals and output data enablesignals, and wherein the data output register further comprises aplurality of latches each receiving a respective differently-phasedinput data enable signal and a respective differently-phased output dataenable signal, the latches being selectively coupled to the data inputterminals responsive to their respective input data enable signals andbeing coupled to the data read output terminals responsive to theirrespective output data enable signals, the output data signals from thedata ports of the array being sequentially stored in each of the latchesand being sequentially transferred from each of the latches to the dataread output terminals after being stored in each of the latches for apredetermined period.
 29. The computer system of claim 28 wherein thetime that the data mask register generates the output signal after thedata mask control signal becomes active corresponds to the predeterminedperiod that the output data signals from the data ports of the array arestored in each of the latches.
 30. A computer system, comprising: aprocessor having a processor data bus, address bus, and control bus; aninput device coupled to the processor; an output device coupled to theprocessor; a memory controller coupled to the processor; and a dynamicrandom access memory having an address bus, at least one data bit line,and a plurality of control lines at least some of which are coupled tothe memory controller, the dynamic random access memory comprising: anarray of memory cells having a plurality of memory cells, a plurality ofrow lines, a plurality of complimentary digit lines, and a pair ofcomplimentary data ports; a row address decoder coupled to the addressbus, the row address decoder adapted to receive a row address on theaddress bus and activate a corresponding one of the row lines of thearray; a column address decoder coupled to the address bus, the columnaddress decoder adapted to receive a column address on the address busand couple a corresponding pair of complimentary digit lines of thearray to respective data ports of the array; and a data path coupledbetween the data ports and a data bit line, the data path including ainput data buffer adapted to convert an input data bit applied to thedata bit line to a corresponding input data signal and a complimentaryinput data signal, and to apply the input data signals to respectivedata ports of the array, and an output data buffer adapted to convert anoutput data signal and a complimentary output data signal applied torespective data ports of the array to an output data bit correspondingto the output data signal, and to apply the output data signal to thedata bit line, the output buffer comprising: a data coder havingcomplimentary data input terminals coupled to the data ports of thearray to receive respective output data signals, a pair of data outputterminals, and a data mask control terminal, the data coder generatingat respective first and second data output terminals complimentary dataread output signals corresponding to complimentary data output signalsapplied to the respective input terminals of the data coder when aninactive data mask control signal is applied to the data mask controlterminal, the data coder generating at the respective first and seconddata output terminals data read output signals having predeterminedvalues when an active data mask control signal is applied to the datamask control terminal, the data coder having a data mask registerincluding the data mask control terminal, the data mask registerreceiving the data mask control signal on the data mask control terminaland a periodic clock signal on a clock input terminal, the registergenerating an output signal responsive to a predetermined portion of theclock signal after the data mask control signal becomes active, the datamask register further including a latency control terminal adapted toreceive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal, the data coder further having adata output register coupled to the data mask register and including thedata input terminals and the data read output terminals, the data coderforcing the data read output signals to have the predetermined valuesresponsive to the output signal from the data mask register; and anoutput stage having respective input terminals coupled to the first andsecond data output terminals of the data coder, the output stagegenerating the output data bit at data bit line that corresponds to thedata read output signals from the data coder when the data read outputsignals do not have the predetermined values, the output stage producinga relatively high impedance at the data bit line when the data readoutput signals have the predetermined values, the output stagecomprising: a first switch coupled between a first voltage node and theoutput data bit; a second switch coupled between a second voltage nodeand the output data bit; and a logic circuit that is structured to closethe first switch responsive to one of the data read signals having thefirst predetermined logic level, open the first switch responsive to theone data read signal having other than the first predetermined logiclevel, close the second switch responsive to the other of the data readsignals having the second predetermined logic level, and open the secondswitch responsive to the other data read signal having other than thesecond predetermined logic level so that the output data bit has a firstlogic level responsive to one of the data read output signals having afirst predetermined logic level, output data bit has a second logiclevel responsive to the other of the data read output signals having asecond predetermined logic level, and the data bit line has therelatively high impedance responsive to both of the read output signalshaving other than the first and second predetermined logic levels.
 31. Adynamic random access memory having an address bus, at least one databit line, and a plurality of control lines, comprising: an array ofmemory cells having a plurality of memory cells, a plurality of rowlines, a plurality of complimentary digit lines, and a pair ofcomplimentary data ports; a row address decoder coupled to the addressbus, the row address decoder adapted to receive a row address on theaddress bus and activate a corresponding one of the row lines of thearray; a column address decoder coupled to the address bus, the columnaddress decoder adapted to receive a column address on the address busand couple a corresponding pair of complimentary digit lines of thearray to respective data ports of the array; and a data path coupledbetween the data ports and a data bit line, the data path including ainput data buffer adapted to convert an input data bit applied to thedata bit line to a corresponding input data signal and a complimentaryinput data signal, and to apply the input data signals to respectivedata ports of the array, and an output data buffer adapted to convert anoutput data signal and a complimentary output data signal applied torespective data ports of the array to an output data bit correspondingto the output data signal, and to apply the output data signal to thedata bit line, the output buffer comprising: a data mask registerincluding a control terminal adapted to receive a DQM signal, the datamask register generating an output signal a predetermined period afterreceipt of the DQM signal, the data mask register further having alatency control terminal adapted to receive a latency control signal,the data mask register altering the time when the data mask registergenerates the output signal as a function of the latency control signal;and a data output receipt coupled to the data mask register andincluding a pair of complimentary data input terminals adapted toreceive complimentary data input signals and a pair of data outputterminals, the data output register generating respective output signalson the data output terminals having predetermined values responsive toreceiving the output signal from the data mask register and havingcomplimentary values corresponding to the data input signals at leastpart of the time that the output signal from the data mask register isnot being received; and an output stage having respective inputterminals coupled to the first and second data output terminals of thedata output register, the output stage generating a data output signalat an output terminal that corresponds to the output signals from thedata output register when the output signals from the data outputregister do not have the predetermined values, the output stageproducing a relatively high impedance at the data output terminal whenthe output signals from the data output register have the predeterminedvalues.
 32. The output buffer of claim 31 wherein the predeterminedvalues of the output signals from the data output register are anyvalues in which the output signals at the respective first and seconddata output terminals have the same value.
 33. The output buffer ofclaim 32 wherein the predetermined values of the output signals from thedata output register correspond to logic “1”.
 34. The output buffer ofclaim 32 wherein the data output register generates the output signalson the respective data output terminals having predetermined valuescontemporaneously with receiving the output signal from the data maskregister.
 35. The output buffer of claim 31 wherein the data maskregister further comprises a latency control terminal adapted to receivea latency control signal, the data mask register altering the time whenthe data mask register generates the output signal as a function of thelatency control signal.
 36. The output buffer of claim 31 wherein thedata output register comprises a multi-phase signal generator receivinga periodic clock signal and generating from the clock signal a pluralityof differently-phased data output enable and data input enable signals,and wherein the data output register further comprises a plurality oflatches each receiving a respective differently-phased data input enablesignal and a respective differently-phased data output enable signal,the latches being selectively coupled to the data input terminals of thedata output register responsive to their respective data input enablesignals and being coupled to the data output terminal responsive totheir respective data output enable signals, the data input signalsbeing sequentially stored in each of the latches and being sequentiallytransferred from each of the latches to the data output terminals afterbeing stored in each of the latches for a predetermined period.
 37. Theoutput buffer of claim 36 wherein the time that the data mask registergenerates the output signal after receiving the DQM signal correspondsto the predetermined period that the data input signals are stored ineach of the latches.
 38. The output buffer of claim 31 wherein theoutput stage comprises a logic circuit that causes the data outputsignal to have a first logic level responsive to one of the outputsignals from the data output register having a first predetermined logiclevel, that causes the data output signal to have a second logic levelresponsive to the other of the output signals from the data outputregister having a second predetermined logic level, and that causes thedata output terminal to have the relatively high impedance responsive toboth of the output signals from the data output register having otherthan the first and second predetermined logic levels.
 39. The outputbuffer of claim 38 wherein the output stage comprises: a first switchcoupled between a first voltage node and the data output terminal; asecond switch coupled between a second voltage node and the data outputterminal; and wherein the logic circuit closes the first switchresponsive to one of the output signals from the data output registerhaving the first predetermined logic level, opens the first switchresponsive to the output signals from the data output register havingother than the first predetermined logic level, closes the second switchresponsive to the other of the output signals from the data outputregister having the second predetermined logic level, and opens thesecond switch responsive to the output signals from the data outputregister having other than the second predetermined logic level.
 40. Anoutput buffer, comprising: a data coder having complimentary data inputterminals, a pair of data read output terminals, and a data mask controlterminal, the data coder generating at respective first and second dataread output terminals complimentary data read output signalscorresponding to complimentary data input signals applied to respectivedata input terminals when an inactive data mask control signal isapplied to the data mask control terminal, the data coder generating atthe respective first and second data read output terminals data readoutput signals having predetermined values when an active data maskcontrol signal is applied to the data mask control terminal, the datacoder having a data mask register, the data mask register including thedata mask control terminal, the data mask register receiving the datamask control signal on the data mask control terminal and a periodicclock signal on a clock input terminal, the register generating anoutput signal responsive to a predetermined portion of the clock signalafter the data mask control signal becomes active, the data maskregister having a latency control terminal adapted to receive a latencycontrol signal, the data mask register altering the time when the datamask register generates the output signal as a function of the latencycontrol signal, the data coder further including a data output registercoupled to the data mask register and having the data input terminalsand the data read output terminals, the data coder forcing the data readoutput signals to have the predetermined values responsive to the outputsignal from the data mask register; and an output stage havingrespective input terminals coupled to the first and second data readoutput terminals of the data coder, the output stage generating a dataoutput signal at an output terminal the corresponds to the data readoutput signals from the data coder when the data read output signals donot have the predetermined values, the output stage producing arelatively high impedance at the data output terminal when the data readoutput signals have the predetermined values, the output stagecomprising: a first switch coupled between a first voltage node and thedata output terminal; a second switch coupled between a second voltagenode and the data output terminal; and a logic circuit that isstructured to close the first switch responsive to one of the data readsignals having the first predetermined logic level, open the firstswitch responsive to the one data read signal having other than thefirst predetermined logic level, close the second switch responsive tothe other of the data read signals having the second predetermined logiclevel, and open the second switch responsive to the other data readsignal having other than the second predetermined logic level.
 41. Theoutput buffer of claim 40 wherein the predetermined values of the dataread output signals are any values in which the data read output signalsat the respective first and second data read output terminals have thesame value.
 42. The output buffer of claim 41 wherein the predeterminedvalues of the data read output buffer correspond to logic “1”.
 43. Theoutput buffer of claim 40 wherein the data coder comprises: a data maskregister including the data mask control terminal, the data maskregister receiving the data mask control signal on the data mask controlterminal and a periodic clock signal on a clock input terminal, theregister generating an output signal responsive to a predeterminedportion of the clock signal after the data mask control signal becomesactive; and a data output register coupled to the data mask register andincluding the data input terminals and the data read output terminals,the data coder forcing the data read output signals to have thepredetermined values responsive to the output signal from the data maskregister.
 44. The output buffer of claim 43 wherein the data maskregister further comprising a latency control terminal adapted toreceive a latency control signal, the data mask register altering thetime when the data mask register generates the output signal as afunction of the latency control signal.
 45. The output buffer of claim43 40 wherein the data output register comprises a multi-phase signalgenerator receiving a periodic clock signal and generating from theclock signal a plurality of differently-phased enable and data inputsignals, and wherein the data output register further comprises aplurality of latches each receiving a respective differently-phasedenable signal and a respective differently-phased data input signal, thelatches being selectively coupled to the data input terminals responsiveto their respective data input signals and being coupled to the dataoutput terminal responsive to their respective enable signals, the datainput signals being sequentially stored in each of the latches and beingsequentially transferred from each of the latches to the data outputterminals after being stored in each of the latches for a predeterminedperiod.
 46. The output buffer of claim 45 wherein the time that the datamask register generates the output signal after the data mask controlsignal becomes active corresponds to the predetermined period that thedata input signals are stored in each of the latches.
 47. A dynamicrandom access memory having an address bus, at least one data bit line,and a plurality of control lines, comprising: an array of memory cellshaving a plurality of memory cells, a plurality of row lines, aplurality of complimentary digit lines, and a pair of complimentary dataports; a row address decoder coupled to the address bus, the row addressdecoder adapted to receive a row address on the address bus and activatea corresponding one of the row lines of the arrays; a column addressdecoder coupled to the address bus, the column address decoder adaptedto receive a column address on the address bus and couple acorresponding pair of complimentary digit lines of the array torespective data ports of the array; and a data path coupled between thedata ports and a data bit line, the data path including a input databuffer adapted to convert an input path bit applied to the data bit lineto a corresponding input data signal and a complimentary input datasignal, and to apply the input data signals to respective data ports ofthe array, and an output data buffer adapted to convert an output datasignal and a complimentary output data signal applied to respective dataports of the array to an output data bit corresponding to the outputdata signal, and to apply the output data signal to the data bit line,the output buffer comprising: a data coder having complimentary datainput terminals coupled to the data ports of the array to receiverespective output data signals, a pair of data output terminals, and adata mask control terminal, the data coder generating at respectivefirst and second data output terminals complimentary data read outputsignals corresponding to complimentary data output signals applied tothe respective input terminals of the data coder when an inactive datamask control signal is applied to the data mask control terminal, thedata coder generating at the respective first and second data outputterminals data read output signals having predetermined values when anactive data mask control signal is applied to the data mask controlterminal, the data coder having a data mask register including the datamask control terminal, the data mask register receiving the data maskcontrol signal on the data mask control terminal and a periodic clocksignal on a clock input terminal, the register generating an outputsignal responsive to a predetermined portion of the clock signal afterthe data mask control signal becomes active, the data mask registerfurther including a latency control terminal adapted to receive alatency control signal, the data mask register altering the time whenthe data mask register generates the output signal as a function of thelatency control signal, the data coder further having a data outputregister coupled to the data mask register and including the data inputterminals and the data read output terminals, the data coder forcing thedata read output signals to have the predetermined values responsive tothe output signal from the data mask register; and an output stagehaving respective input terminals coupled to the first and second dataoutput terminals of the data coder, the output stage generating theoutput data bit at data bit line that corresponds to the data readoutput signals from the data coder when the data read output signals donot have the predetermined values, the output stage producing arelatively high impedance at the data bit line when the data read outputsignals have the predetermined values, the output stage comprising: afirst switch coupled between a first voltage node and the output databit; a second switch coupled between a second voltage node and theoutput data bit; and a logic circuit that is structured to close thefirst switch responsive to one of the data read signals having the firstpredetermined logic level, open the first switch responsive to the onedata read signal having other than the first predetermined logic level,close the second switch responsive to the other of the data read signalshaving the second predetermined logic level, and open the second switchresponsive to the other data read signal having other than the secondpredetermined logic level.
 48. The dynamic random access memory of claim47 wherein the predetermined values of the data read output signals areany values in which the data read output signals at the respective dataoutput terminals of the data coder have the same value.
 49. The dynamicrandom access memory of claim 48 wherein the predetermined values of thedata read output signal correspond to logic “1”.
 50. The dynamic randomaccess memory of claim 47 wherein the data coder comprises: a data maskregister including the data mask control terminal, the data maskregister receiving the data mask control signal on the data mask controlterminal and a periodic clock signal on a clock input terminal, theregister generating an output signal responsive to a predeterminedportion of the clock signal after the data mask control signal becomesactive; and a data control register coupled to the data mask registerand including the data input terminals and the data read outputterminals, the data coder forcing the data read output signals to havethe predetermined values responsive to the output signal from the datamask register.
 51. The dynamic random access memory of claim 50 whereinthe data mask register further comprises a latency control terminaladapted to receive a latency control signal, the data mask registeraltering the time when the data mask register generates the outputsignal as a function of the latency control signal.
 52. The dynamicrandom access memory of claim 50 47 wherein the data output registercomprises a multi-phase signal generator receiving a periodic clocksignal and generating from the clock signal a plurality ofdifferently-phased input data enable signals and output data enablesignals, and wherein the data output register further comprises aplurality of latches each receiving a respective differently-phasedinput data enable signal and a respective differently-phased output dataenable signal, the latches being selectively coupled to the data inputterminals responsive to their respective input data enable signals andbeing coupled to the data read output terminals responsive to theirrespective output data enable signals, the output data signals from thedata ports of the array being sequentially stored in each of the latchesand being sequentially transferred from each of the latches to the dataread output terminals after being stored in each of the latches for apredetermined period.
 53. The dynamic random access memory of claim 52wherein the time that the data mask register generates the output signalafter the data mask control signal becomes active corresponds to thepredetermined period that the output data signals from the data ports ofthe array are stored in each of the latches.
 54. A method of maskingdata coupled through a data output buffer responsive to a data masksignal applied to the output buffer, the output buffer having first andsecond stages connected in series with each other, the methodcomprising: registering a signal representing the data mask signal inresponse to a first clock edge of a clock signal for a first latencysetting and in response to a second clock edge of the clock signal for asecond latency setting; coupling first and second input terminals atwhich complimentary first and second data signals are applied,respectively, to respective first and second output terminals of thefirst stage when the data mask signal is inactive; generating a controlsignal responsive to a predetermined portion of a clock signal after thedata mask signal becomes active; applying respective predeterminedsignals to the first and second output terminals of the first stageresponsive to the control signal; applying a data output signal to anoutput terminal of the second stage corresponding to the complimentaryfirst and second data signals when the respective predetermined signalsare not being applied to the first and second input terminals of thesecond stage; and tri-stating the output terminal of the second stagewhen the respective predetermined signals are being applied to the firstand second input terminals of the second stage.
 55. The method of claim54 wherein the respective predetermined signals applied to the first andsecond output terminals of the first stage are any signals that are notcomplimentary to each other.
 56. The method of claim 55 wherein thepredetermined signals correspond to logic “1”.
 57. The method of claim54 wherein the coupling of the first and second input terminals to therespective first and second output terminals of the first stage isdelayed in time so that the complimentary first and second data signalsare stored in the first stage for a predetermined time.
 58. A method ofselectively masking complimentary read data signals responsive to a datamask signal, comprising: registering a signal representing the data masksignal in response to a first clock edge of a clock signal for a firstlatency setting and in response to a second clock edge of the clocksignal for a second latency setting; generating coded read data signalscorresponding to the complimentary read data signals in the absence ofthe data mask signal; a predetermined period after receipt of the datamask signal, generating coded read data signals coded in a predeterminedmanner responsive to the data mask signal; generating on a data outputterminal an output signal having a value corresponding to the coded readdata signals if the coded read data signals are not coded in thepredetermined manner; and placing the data output terminal at a highimpedance if the coded read data signals are coded in the predeterminedmanner.
 59. The method of claim 58 wherein the predetermined manner ofcoding is for the coded read data signals to have the same value.
 60. Amethod of masking data coupled through a data output buffer responsiveto a data mask signal applied to the output buffer, the output bufferhaving first and second stages connected in series with each other, themethod comprising: registering a signal representing the data masksignal in response to a first clock edge of a clock signal for a firstlatency setting and in response to a second clock edge of the clocksignal for a second latency setting; coupling first and second inputterminals at which complimentary first and second data signals areapplied, respectively, to respective first and second output terminalsof the first stage to provide first and second read output signals,respectively, to the second stage when the data mask signal is inactive;applying respective predetermined signals to the first and second outputterminals of the first stage to provide the first and second read outputsignals, respectively, to the second stage when the data mask signal isactive; coupling an output terminal of the second stage to a firstvoltage node responsive to one of the data read output signals having afirst predetermined logic level; coupling the output terminal of thesecond stage to a second voltage node responsive to the other of thedata read output signals having a second predetermined logic level; andelectrically isolating the output terminal of the second stage from thefirst and second voltage nodes responsive to both the data read outputsignals having other than the first or second predetermined logiclevels.
 61. The method of claim 60 wherein the respective predeterminedsignals applied to the first and second output terminals of the firststage are any signals that are not complimentary to each other.
 62. Themethod of claim 61 wherein the predetermined signals correspond to logic“1”.
 63. The method of claim 60 wherein the coupling of the first andsecond input terminals to the respective first and second outputterminals of the first stage is delayed in time so that thecomplimentary first and second data signals are stored in the firststage for a predetermined time.
 64. A method of selectively maskingcomplimentary read data signals responsive to a data mask signal,comprising: registering a signal representing the data mask signal inresponse to a first clock edge of a clock signal for a first latencysetting and in response to a second clock edge of the clock signal for asecond latency setting; generating first and second coded read datasignals corresponding to the complimentary read data signals,respectively, in the absence of the data mask signal; coding the firstand second coded read data signals in a predetermined manner responsiveto the data mask signal; coupling a data output terminal to a firstvoltage node responsive to one of the coded read data signals having afirst predetermined logic level; coupling the data output terminal to asecond voltage node responsive to the other of the coded read datasignals having a second predetermined logic level; and electricallyisolating the data output terminal from the first and second voltagenodes if the coded read data signals are coded in the predeterminedmanner.
 65. The method of claim 64 wherein the predetermined manner ofcoding is for the coded read data signals to have the same value.
 66. Amethod of selectively masking complimentary read data signals responsiveto a data mask signal, comprising: registering a signal representing thedata mask signal in response to a first clock edge of a clock signal fora first latency setting and in response to a second clock edge of theclock signal for a second latency setting; generating coded read datasignals corresponding to the complimentary read data signals in theabsence of the data mask signal; generating coded read data signalscoded in a predetermined manner responsive to the data mask signal;coupling a data output terminal to a first voltage node responsive toone of the coded read data signals having a first predetermined logiclevel; coupling the data output terminal to a second voltage noderesponsive to the other of the coded read data signals having a secondpredetermined logic level; and electrically isolating the data outputterminal from the first and second voltage nodes if the coded read datasignals are coded in the predetermined manner.
 67. The method of claim66 wherein the predetermined manner of coding is for the coded read datasignals to have the same value.